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1CY 7C13 2/ CY7C1 36
fax id: 5201
CY7C132/CY7C136 CY7C142/CY7C146
2Kx8 Dual-Port Static RAM
Features
* True Dual-Ported memory cells which allow simultaneous reads of the same memory location * 2K x 8 organization * 0.65-micron CMOS for optimum speed/power * High-speed access: 15 ns * Low operating power: ICC = 90 mA (max.) * Fully asynchronous operation * Automatic power-down * Master CY7C132/CY7C136 easily expands data bus width to 16 or more bits using slave CY7C142/CY7C146 * BUSY output flag on CY7C132/CY7C136; BUSY input on CY7C142/CY7C146 * INT flag for port-to-port communication (52-pin PLCC/PQFP versions) * Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and 52-pin TQFP (CY7C136/146) * Pin-compatible and functionally equivalent to IDT7132/IDT7142
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are high-speed CMOS 2K by 8 dual-port static RAMs. Two ports are provided to permit independent access to any location in memory. The CY7C132/ CY7C136 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs. Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C132/CY7C142 are available in 48-pin DIP. The CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
R/WL CEL OEL
Pin Configuration
R/WR CER OER CEL R/WL BUSYL A10L OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND
DIP Top View
1 2 3 4 5 6 7 8 9 10 11 12 7C132 13 7C142 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VCC CER R/WR BUSYR A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R C132-2
I/O7L I/O0L BUSYL[1] A 10L A 0L
I/O CONTROL
I/O CONTROL
I/O7R I/O0R BUSYR[1]
ADDRESS DECODER
MEMORY ARRAY
ADDRESS DECODER
A 10R A 0R
CEL OEL R/WL INTL[2]
ARBITRA TION LOGIC (7C132/7C136 ONLY) AND INTERRUPTLOGIC (7C136/7C146 ONLY)
CER OER R/WR INTR[2] C132-1
Notes: 1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor. CY7C142/CY7C146 (Slave): BUSY is input. 2. Open drain outputs; pull-up resistor required.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose * CA 95134 * 408-943-2600 December 1989 - Revised March 27, 1997
CY7C132/CY7C136 CY7C142/CY7C146
Pin Configurations (continued)
PLCC Top View PQFP Top View
A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L
8 9 10 11 12 13 14 15 16 17 18 19 20
7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C136 40 7C146 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33
OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R
52 51 50 49 48 47 46 45 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 7C136 33 7C146 32 31 30 29 28 27 1415 16 17 18 19 20 21 22 23 24 25 26 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R C132-4
C132-3
Selection Guide
7C132-25[3] 7C136-25 7C136-15[3,4] 7C142-25 7C146-25 7C146-15 15 25 190 170 7C132-30 7C136-30 7C142-30 7C146-30 30 170 7C132-35 7C136-35 7C142-35 7C146-35 35 120 170 75 65 65 45 65 7C132-45 7C136-45 7C142-45 7C146-45 45 90 120 35 45 7C132-55 7C136-55 7C142-55 7C146-55 55 90 120 35 45
Maximum Access Time (ns) Maximum Operating Com'l/Ind Current (mA) Maximum Operating Military Current (mA) Maximum Standby Com'l/Ind Current (mA) Military
Notes: 3. 15 and 25-ns version available in PQFP and PLCC packages only. 4. Shaded area contains preliminary information.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage to Ground Potential (Pin 48 to Pin 24).................................................-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State .....................................................-0.5V to +7.0V DC Input Voltage .................................................-3.5V to +7.0V Output Current into Outputs (LOW) ............................. 20 mA
]
Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... >200 mA
Operating Range
Range Commercial Industrial Military[5] Ambient Temperature 0C to +70C -40C to +85C -55C to +125C VCC 5V 10% 5V 10% 5V 10%
Note: 5. TA is the "instant on" case temperature.
2
CY7C132/CY7C136 CY7C142/CY7C146
Electrical Characteristics Over the Operating Range[6]
7C132-30[3] 7C136-25,30 7C142-30 7C136-15[3,4] 7C146-25,30 7C146-15 Parameter Description VOH VOL VIH VIL IIX IOZ IOS ICC Test Conditions Min. 2.4 0.4 0.5 2.2 0.8 GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max., VOUT = GND CE = VIL, Outputs Open, f = fMAX[9] Com'l Mil 75 65 -5 -5 +5 +5 -350 190 -5 -5 2.2 0.8 +5 +5 -350 170 -5 -5 Max. Min. 2.4 0.4 0.5 2.2 0.8 +5 +5 -350 120 170 45 65 135 115 90 115 15 15 15 15 125 105 85 105 -5 -5 Max. Output HIGH Voltage VCC = Min., IOH = -4.0 mA Output LOW Voltage IOL = 4.0 mA IOL = 16.0 mA[7] Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[8] VCC Operating Supply Current Standby Current Both Ports, TTL Inputs Standby Current One Port, TTL Inputs Standby Current Both Ports, CMOS Inputs Standby Current One Port, CMOS Inputs 7C132-35 7C136-35 7C142-35 7C146-35 Min. Max. 2.4 0.4 0.5 2.2 0.8 +5 +5 -350 90 120 35 45 75 90 15 15 70 85 mA mA mA mA 7C132-45,55 7C136-45,55 7C142-45,55 7C146-45,55 Min. 2.4 0.4 0.5 V V A A mA mA Max. Unit V V
ISB1
CEL and CER > VIH, Com'l f = fMAX[9] Mil CEL or CER > VIH, Com'l Active Port Outputs Mil Open, [9] f = fMAX Both Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0 One Port CEL or CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[9] Com'l Mil Com'l Mil
ISB2
ISB3
ISB4
]
Capacitance[10]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 15 10 Unit pF pF
Notes: 6. See the last page of this specification for Group A subgroup testing information. 7. BUSY and INT pins only. 8. Duration of the short circuit should not exceed 30 seconds. 9. At f=fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/trc and using AC Test Waveforms input levels of GND to 3V. 10. This parameter is guaranteed but not tested.
3
CY7C132/CY7C136 CY7C142/CY7C146
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIGAND SCOPE R2 347 R1893 5V OUTPUT 5 pF INCLUDING JIGAND SCOPE R2 347
C132-5
R1893
5V 281
BUSY OR INT
30pF
(a)
(b)
C132-6
BUSYOutput Load (CY7C132/CY7C136 ONLY)
ALL INPUT PULSES
Equivalent to:
THVENIN EQUIVALENT 3.0V 250 1.4V 10%
90%
OUTPUT
GND
90% 10% < 5 ns
< 5 ns
]
Switching Characteristics Over the Operating Range[6, 11]
7C136-15[3,4] 7C146-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Read Cycle Time Address to Data CE LOW to Data OE LOW to Low CE LOW to Low CE LOW to CE HIGH to CYCLE[15] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z [10] R/W HIGH to Low Z [10] 0 15 12 12 2 0 12 10 0 10 0 25 20 20 2 0 15 15 0 15 0 30 25 25 2 0 25 15 0 15 ns ns ns ns ns ns ns ns ns ns Valid[12] 0 15 10 3 10 3 10 0 15 0 25 5 15 0 25 3 15 5 15 Valid[12] Z[10, 13] Z[10, 13, 14] Z[10, 13] Data Hold from Address Change OE LOW to Data Valid[12] OE HIGH to High 15 15 0 25 15 3 15 25 25 0 30 20 30 30 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 7C132-30 7C136-30 7C142-30 7C146-30 Min. Max. Unit
CE HIGH to High Z[10, 13, 14] Power-Up[10] Power-Down[10]
4
CY7C132/CY7C136 CY7C142/CY7C146
Switching Characteristics Over the Operating Range[6, 11] (continued)
7C136-15[3,4] 7C146-15 Parameter BUSY/INTERRUPT TIMING tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[16] 5 0 13 15 Note 18 Note 18 15 15 15 15 15 15 Port Set Up for Priority R/W LOW after BUSY LOW[17] R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay Mismatch[16] 15 15 15 15 5 0 20 25 Note 18 Note 18 25 25 25 25 25 25 20 20 20 20 5 0 30 30 Note 18 Note 18 25 25 25 25 25 25 20 20 20 20 ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C132-25[3] 7C136-25 7C142-25 7C146-25 Min. Max. 7C132-30 7C136-30 7C142-30 7C146-30 Min. Max. Unit
INTERRUPT TIMING[19] tWINS tEINS tINS tOINR tEINR tINR R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset CE to INTERRUPT Reset Time[16] Time[16] ns ns ns ns ns ns
Address to INTERRUPT Reset Time[16]
Switching Characteristics Over the Operating Range[6, 11]
7C132-35 7C136-35 7C142-35 7C146-35 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Read Cycle Time Address to Data CE LOW to Data OE LOW to Low CE LOW to Low CE LOW to CE HIGH to Valid[12] 0 35 20 3 20 5 20 0 35 0 35 5 20 0 35 3 20 5 25 Valid[12] Z[10, 13] Z[10, 13, 14] Z[10, 13] Data Hold from Address Change OE LOW to Data Valid[12] OE HIGH to High 35 35 0 45 25 3 25 45 45 0 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C132-45 7C136-45 7C142-45 7C146-45 Min. Max. 7C132-55 7C136-55 7C142-55 7C146-55 Min. Max. Unit
CE HIGH to High Z[10, 13, 14] Power-Up[10] Power-Down[10]
5
CY7C132/CY7C136 CY7C142/CY7C146
Switching Characteristics Over the Operating Range[6, 11] (continued)
7C132-35 7C136-35 7C142-35 7C146-35 WRITE CYCLE[15] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE tBLA tBHA tBLC tBHC tPS tWB tWH tBDD tDDD tWDD Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start R/W Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z [10] R/W HIGH to Low Z [10] BUSY LOW from Address Match BUSY HIGH from Address BUSY LOW from CE LOW BUSY HIGH from CE HIGH[16] Port Set Up for Priority R/W LOW after BUSY LOW[17] R/W HIGH after BUSY HIGH BUSY HIGH to Valid Data Write Data Valid to Read Data Valid Write Pulse to Data Delay 5 0 30 35 Note 18 Note 18 25 25 25 25 25 25 Mismatch[16] 0 20 20 20 20 5 0 35 45 Note 18 Note 18 35 35 35 35 35 35 35 30 30 2 0 25 15 0 20 0 25 25 25 25 5 0 35 45 Note 18 Note 18 45 45 45 45 45 45 45 35 35 2 0 30 20 0 20 0 30 30 30 30 55 40 40 2 0 30 20 0 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7C132-45 7C136-45 7C142-45 7C146-45 7C132-55 7C136-55 7C142-55 7C146-55
BUSY/INTERRUPT TIMING
INTERRUPT TIMING[19] tWINS tEINS tINS tOINR tEINR tINR R/W to INTERRUPT Set Time CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[16] CE to INTERRUPT Reset Time[16] Address to INTERRUPT Reset Time[16] ns ns ns ns ns ns
Notes: 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30-pF load capacitance. 12. AC test conditions use VOH = 1.6V and VOL = 1.4V. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE, and tHZWE are tested with CL = 5pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 15. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 17. CY7C142/CY7C146 only. 18. A write operation on Port A, where Port A has priority, leaves the data on Port B's outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B's address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 19. 52-pin PLCC and PQFP versions only.
6
CY7C132/CY7C136 CY7C142/CY7C146
Switching Waveforms
Read Cycle No. 1 (Either Port-Address Access) [20, 21]
tRC ADDRESS tOHA DATA OUT PREVIOUS DA VALID TA tAA DATA VALID
C132-7
Read Cycle No. 2 (Either Port-CE/OE)
[20, 22]
CE OE tACE tDOE tHZOE tHZCE
tLZOE tLZCE DATA OUT tPU ICC ISB
DATA VALID tPD
C132-8
Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136)
n
tRC ADDRESS R R/WR DINR tPS ADDRESS L BUSYL tBLA DOUTL tWDD
Notes: 20. R/W is HIGH for read cycle. 21. Device is continuously selected, CE = VIL and OE = VIL. 22. Address valid prior to or coincident with CE transition LOW.
ADDRESS MATCH tPWE
VALID
ADDRESS MATCH tBHA tBDD VALID tDDD
C132-9
7
CY7C132/CY7C136 CY7C142/CY7C146
Switching Waveforms (continued)
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)[15, 23]
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN DATA VALID tHD tAW tHA tPWE
OE tHZOE HIGH IMPEDANCE DOUT
C132-10
Write Cycle No. 2 (R/W Three-States Data I/Os-Either Port)[15, 24]
tWC ADDRESS tSCE CE tSA R/W tSD DATAIN tHZWE DOUT
C132-11
tHA
tAW
tPWE
tHD
DATA VALID tLZWE HIGH IMPEDANCE
Notes: 23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
8
CY7C132/CY7C136 CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First:
ADDRESS L,R CEL tPS CER tBLC BUSYR
C132-12
ADDRESS MATCH
tBHC
CER Valid First:
ADDRESS L,R CER tPS CEL
ADDRESS MATCH
tBLC BUSY L
tBHC
C132-13
Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First:
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSY R
C132-14
ADDRESS MISMATCH
tBHA
Right Address Valid First:
tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSY L
C132-15
ADDRESS MISMATCH
tBHA
9
CY7C132/CY7C136 CY7C142/CY7C146
Switching Waveforms (continued)
Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)
CE
tPWE R/W tWB BUSY tWH
C132-16
Interrupt Timing Diagrams[19]
Left Side Sets INTR:
tWC ADDRESS L CEL R/WL tSA INTR tINS WRITE 7FF tHA
tEINS
tWINS
C132-17
Right Side Clears INTR:
tRC ADDRESS R tHA CER tEINR R/WR READ 7FF tINR
OER tOINR INTR
C132-18
10
CY7C132/CY7C136 CY7C142/CY7C146
Interrupt Timing Diagrams[19] (continued)
Right Side Sets INTL:
tWC ADDRESS R tINS CER tEINS R/WR INTL tSA tWINS WRITE 7FE tHA
C132-19
Right Side Clears INTL:
tRC ADDRESSL CEL tEINR R/WL OEL tOINR INTL
C132-20
READ 7FE tHA tINR
11
CY7C132/CY7C136 CY7C142/CY7C146
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 1.2 1.0 0.8 0.6 0.6 0.4 0.2 0.0 4.0 4.5 5.0 ISB3 5.5 6.0 0.4 0.2 0.6 -55 25 VCC =5.0V VIN =5.0V 60 40 20 0 125 0 1.0 2.0 3.0 4.0 AMBIENTTEMPERATURE(C) OUTPUTVOLTAGE(V) VCC =5.0V TA =25C ICC 1.2 1.0 0.8 ICC NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 120 100 80 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE
ISB3
SUPPLYVOLTAGE(V)
NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 1.3 1.2 1.1 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 TA =25C 1.0 1.6 1.4
NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 140 120 100 1.2 80 60 VCC =5.0V 0.8 0.6 -55 40 20 25 125
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
VCC =5.0V TA =25C 1.0 2.0 3.0 4.0
0 0.0
SUPPLYVOLTAGE(V)
AMBIENTTEMPERATURE(C)
OUTPUTVOLTAGE(V)
TYPICAL POWER- ON CURRENT vs. SUPPLY VOLTAGE 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1.0 2.0 3.0 4.0 5.0 30.0 25.0 20.0 15.0 10.0 5.0 0
TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25
NORMALIZED I CC vs. CYCLE TIME VCC =5.0V TA =25C VIN =0.5V 1.0
0.75 VCC =4.5V TA =25C 0 200 400 600 800 1000 0.50 10 20 30 40
SUPPLYVOLTAGE(V)
CAPACITANCE(pF)
CYCLE FREQUENCY (MHz)
12
CY7C132/CY7C136 CY7C142/CY7C146
Ordering Information
Speed (ns) 30 35 Ordering Code CY7C132-30PC CY7C132-30PI CY7C132-35PC CY7C132-35PI CY7C132-35DMB 45 CY7C132-45PC CY7C132-45PI CY7C132-45DMB 55 CY7C132-55PC CY7C132-55PI CY7C132-55DMB Speed (ns) 15 25 30 Ordering Code CY7C136-15JC CY7C136-15NC CY7C136-25JC CY7C136-25NC CY7C136-30JC CY7C136-30NC CY7C136-30JI 35 CY7C136-35JC CY7C136-35NC CY7C136-35JI CY7C136-35LMB 45 CY7C136-45JC CY7C136-45NC CY7C136-45JI CY7C136-45LMB 55 CY7C136-55JC CY7C136-55NC CY7C136-55JI CY7C136-55LMB
Shaded area contains preliminary information.
Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 Package Name J69 N52 J69 N52 J69 N52 J69 J69 N52 J69 L69 J69 N52 J69 L69 J69 N52 J69 L69
Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier
Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military
13
CY7C132/CY7C136 CY7C142/CY7C146
Ordering Information (continued)
Speed (ns) 30 35 Ordering Code CY7C142-30PC CY7C142-30PI CY7C142-35PC CY7C142-35PI CY7C142-35DMB 45 CY7C142-45PC CY7C142-45PI CY7C142-45DMB 55 CY7C142-55PC CY7C142-55PI CY7C142-55DMB Speed (ns) 15 25 30 Ordering Code CY7C136-15JC CY7C136-15NC CY7C146-25JC CY7C146-25NC CY7C146-30JC CY7C146-30NC CY7C146-30JI 35 CY7C146-35JC CY7C146-35NC CY7C146-35JI CY7C146-35LMB 45 CY7C146-45JC CY7C146-45NC CY7C146-45JI CY7C146-45LMB 55 CY7C146-55JC CY7C146-55NC CY7C146-55JI CY7C146-55LMB
Shaded area contains preliminary information.
Package Name P25 P25 P25 P25 D26 P25 P25 D26 P25 P25 D26 Package Name J69 N52 J69 N52 J69 N52 J69 J69 N52 J69 L69 J69 N52 J69 L69 J69 N52 J69 L69
Package Type 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Molded DIP 48-Lead (600-Mil) Sidebraze DIP Package Type 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Pin Plastic Quad Flatpack 52-Lead Plastic Leaded Chip Carrier 52-Square Leadless Chip Carrier
Operating Range Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Military Commercial Industrial Military Commercial Industrial Military
14
CY7C132/CY7C136 CY7C142/CY7C146
MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics
Parameter VOH VOL VIH VIL Max. IIX IOZ ICC ISB1 ISB2 ISB3 ISB4 Subgroups 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Switching Characteristics
Parameter READ CYCLE tRC tAA tACE tDOE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tBLA tBHA tBLC tBHC tPS tWINS tEINS tINS tOINR tEINR tINR BUSY TIMING tWB[25] tWH tBDD 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 7, 8, 9, 10, 11 Subgroups
BUSY/INTERRUPT TIMING
Note: 25. CY7C142/CY7C146 only.
Document #: 38-00061-K
15
CY7C132/CY7C136 CY7C142/CY7C146
Package Diagrams
48-Lead (600-Mil) Sidebraze DIP D26
52-Lead Plastic Leaded Chip Carrier J69
16
CY7C132/CY7C136 CY7C142/CY7C146
Package Diagrams (continued)
52-Square Leadless Chip Carrier L69
52-Lead Plastic Quad Flatpack N52
17
CY7C132/CY7C136 CY7C142/CY7C146
Package Diagrams (continued)
48-Lead (600-Mil) Molded DIP P25
(c) Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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